Electrical-Optical (E-O) interfaces are used in high-speed communication systems to convert an electrical signal into an optical signal. Typically, the E-O interface core includes a modulator configured to generate a modulated light power as a function of an electrical signal, and a driver, receiving, at the input, the electrical signal from preceding electronic stages and driving the modulator with voltage and current of sufficient magnitudes.
The driver may be particularly important in relatively high data rate applications since it provides relatively large output voltage levels with steep rising and falling edges for proper operation of the modulator and with limited jitter so as to not degrade the transmitted bit stream. At the same time, it may be desirable that the driver be designed to reduce its power consumption, since it contributes significantly to the overall power budget of a typical optical link.
In the specific case of Mach Zehnder Modulators (MZMs), due to the geometrical size of the interferometer used to build the MZM, for high speed operation, the driver is often split into several stages, each driving a portion of the MZM, thus forming a distributed modulating structure. In this case, it may be desirable that the driver stages allow their intrinsic delays to be programmed for proper operation of the distributed architecture by equalizing the optical delay of the light propagating within the MZM optical guides with the delay of the electrical signal propagating through the multiple stages of the distributed driver.
For high speed operation, a common high speed driver architectures includes travelling wave amplifiers with a termination load. (See for example, “Design of an opto-electronic modulator driver amplifier for 40-Gb/s data rate systems,” Long, A., Buck, J., and Powell, R., Lightwave Technology Journal, Volume 20, (2002), Pages 2015-2021, and “Ultra-low voltage substrate-removed mach-zehnder intensity modulators with integrated electrical drivers,” Dogru, S., JaeHyuk Shin, and Dagli, N., LEOS Annual Meeting Conference Proceedings, 2009, LEOS '09, IEEE, (2009), Pages 656-657). However, this kind of architecture generally suffers from a high power dissipation, part of which is wasted in the termination load.
Recently, alternative approaches that avoid a travelling wave architecture and based on cascaded delay stages have been proposed. (See, for example, U.S. Pat. Nos. 7,899,276, 7,515,775, 7,450,787 to Kucharski et al., and U.S. Pat. No. 7,039,258 to Gunn, III et al.). However, their use in high speed applications may be limited by the intrinsic structure of the modulator. In fact, the higher the operating data rate, the shorter each modulator stage should be to reduce the electrical length of its electrodes and thus improve the propagation of the electrical driving signal throughout the electrode length, even in the absence of a termination load. Reducing the length of each modulator stage, i.e. increasing the number of stages for a given total length, may include the formation of proportionally reduced delays between one stage and the following one. However, cascaded passive delay elements typically suffer from non-negligible losses, in particular, when integrated on-chip, and thus may introduce significant attenuation on the propagating signal. On the other hand, the intrinsic delay of active delay elements may be technologically limited and may not be arbitrarily reduced for a given integration technology, thus setting an upper limit to the operating data rate of these approaches.